TSMC (TSE: 2330)

As of the time of writing , the author held shares of TSMC and BE Semiconductor. This may have changed since. This post is not investment advice and the readers should do their own research and exercise judgment before making any investment decisions.

Business Description

TSMC is the world’s largest outsourced manufacturer (foundry) of semiconductors with ~60% market share. Its customers, mostly but not exclusively companies without fabrication facilities (hence “fabless”), develop their own chip designs, which TSMC uses to fabricate chips on silicon wafers. The company generated 89% of its FY21 revenue through the sale of these wafers, out of which the semiconductors are diced and packaged into finished chips. Design, packaging, testing services and royalty-generating IP contributed the other 11% of revenue.

79% of TSMC’s FY21 revenues came from its 10 largest customers (including AMD, Apple, Broadcom, MediaTek, Nvidia, Qualcomm). Most of these customers’ designs utilize the most advanced manufacturing processes (leading-edge), which only Intel, Samsung, and TSMC have mastered. TSMC is arguably a monopoly in the most advanced of leading-edge processes (TSMC’s 5nm process).

Semiconductor fabrication is capital-intensive and that intensity is rising. TSMC’s capex/sales has averaged c. 40% for the past decade, and the company’s capex plans suggest the next 4 years' average could climb to 50% through 2025. However, semiconductor fabrication is also incredibly difficult, particularly at the leading-edge, and commands appropriate pricing. Hence, that capital has produced outstanding returns: TSMC’s RoIC averaged ~26% over the past decade as operating income has compounded at ~16.5% (the discrepancy is due to TSMC paying around half of net income in dividends, likely because of its Taiwanese retail shareholders). The average also masks TSMC’s investment cycles, at the peak of which capex has reached half of sales and has subsequently subsided to about a third at the bottom. 2011 marked an investment peak, and TSMC has compounded free cash flow to equity per share at 23% since.

Why It’s Interesting

In January 2021, TSMC’s management presented their forecasts/plans for revenue, gross and operating margins, and capex for the next several years (through 2025). The revenue forecasts have since been reaffirmed, then revised upwards, the margin goals have been reaffirmed, while the capex plans, though not explicitly reaffirmed beyond 2022, appear to remain in place. On the 1Q22 earnings call, management updated their FY22 guidance, “… we expect full year growth to likely be at or exceed the high end of our guidance range of mid- to high-20s percent in U.S. dollar terms.” The previous guidance of $40bn-$44bn capex in 2022, a 15%-20% sales CAGR “over the next several years” (initially 2021-2025), and a “long-term gross margin of 53% and higher,” and ROE of 25% seem to remain in place.

If TSMC’s goals are achieved, the company will likely have maintained or extended its technological leadership. This would in turn mean it would have plenty of opportunities to compound earnings beyond “the next several years.” At the lower end of the forecasts – 15% 2021-2025 CAGR, 53% gross margins, 40% operating margins – TSMC would earn ~NT$1.1tn in EBIT in FY25. This would cost it close to NT$1tn in cumulative capex during the period, and, assuming the capex is front-loaded, FY25 capex would be 35% of sales. The rate of return on these investments is expected to be quite satisfactory, and unlevered free cash flow could compound at a 23% 2021-2025 CAGR to close to NT$610bn.

One path to the lower end of the revenue forecast interval is illustrated in the table below. This is not my estimate of TSMC’s results. It is simply an illustration of one way to get to management’s forecast, including an industry downturn in 2023 which would lead to TSMC’s first revenue contraction since 2009.

Though conventional wisdom advises against investing in businesses with large capex requirements during periods of high inflation, TSMC expects to achieve returns on those investments that are in line with its exceptional historical RoIC and thus avoid being, to quote Buffett, “swindled” by inflation. This can only be achieved if the company has a significant competitive advantage and value proposition to its customers that would allow it to charge sufficiently high prices. These will be discussed later.

Exhibit 1: One path to a 15% 2021-2025 CAGR; amounts are in millions of NT$, assumptions are in orange

Source: Company filings, earnings call transcripts

Assuming all this is clearly visible at the end of 2024 and TSMC trades at a multiple of 15x-20x EV to FY25 (or NTM) NOPAT, in 2.5 years, the company would be worth NT$15.2tn-NT$20.3tn in EV or NT$15.4tn-NT$20.4tn in MV (with a few minor assumptions on net debt and other net liabilities) and would have maybe paid NT$1tn in dividends along the way. A 15x-20x EV/NTM NOPAT could be arrived at by capitalizing TSMC as a perpetuity with a discount rate of 10% and a grow rate of 3%-5%, respectively; a fairly conservative set of assumptions (see Some Base Rates).

The company is worth ~NT$13.4tn in MV today, meaning there is a potential for IRRs of 10% (with a 15x multiple) to 24% (with a 20x multiple) if one believes this scenario is highly probable. If TSMC’s results turn out better and reach the high end of guidance (20% ‘21-‘25 revenue CAGR), maintaining the same multiples would result in IRRs of 18% to 33%.

One obviously needs to look beyond 2025 to assess the value of the company, as do TSMC’s management when planning capacity.

The forecasts made by TSMC’s management are as credible as those of any semiconductor industry forecaster. The reason – TSMC is the major foundry of all fabless companies utilizing leading-edge manufacturing. These companies, which compete with each other, submit their own forecasts to TSMC so that TSMC can plan its capacity. TSMC’s management then use all of these forecasts and all other proprietary information about its customers to assemble their own information mosaic and arrive at their own forecast. The fact that TSMC, operating in the most capex-intensive segment of a very cyclical industry, has not burned cash on a free cash flow basis this century should lend the management’s forecasts some credibility.

Yet, judging by these prospective rates of return, the market does not seem to be pricing in any of the above scenarios as very likely. If a company’s price is the probability-weighted sum of the present values of cash flows under different scenarios, it appears the market is currently pricing management’s forecasts for the next several years as highly improbable and/or fairly bleak growth prospects long-term.

Implied probabilities are of course based on a number of assumptions, but what seems to be objectively true is that the market has been growing more pessimistic on TSMC’s prospects since management first presented its longer-term forecast in January 2021 – the share price has been flat, despite the forecast’s upward revisions, and the company’s EV/NTM EBIT multiple has contracted almost 35%.

Exhibit 2: TSMC’s EV/NTM EBIT

Source: TIKR

Part of this can be attributed to the broader tech/high-duration asset sell-off that started in November 2021, but the stock had underperformed the semiconductor sector before that, and there have been some company-specific risks that probably grew prominent in the minds of investors. I would speculate that the market’s lack of conviction in TSMC’s growth prospects can broadly be attributed to:

1. Concerns about the strength of future semiconductor demand – how much of the current demand is “real” rather than mere inventory replenishment and build-up and, hence, when would an inventory glut appear and how severe would it be;

2. Concerns about the plans of enormous supply capacity additions – the automotive semiconductor shortages sparked a wave of semiconductor manufacturing onshoring initiatives, and Russia’s insane invasion of Ukraine only added fuel to the fire by heightening fears of a Chinese invasion of Taiwan.

TSMC’s capex plans for the next several years and those of its two primary competitors, Intel’s and Samsung’s foundry businesses, suggest a huge amount of leading-edge capacity will be added over the next few years. Based on the three companies’ capex plans, I roughly estimate they could add leading-edge wafer capacity equivalent to TSMC’s 2021 total 2021 wafer capacity (estimates are in the Risks section) through 2025. In addition, other IDMs and foundries have announced capacity expansion plans in response to the current shortages. Consultancy IC Insights estimates sub-10nm capacity will quadruple over the next four years.

The political push behind onshoring only worsened the fears that pro-cyclical supply additions at what seems like a cycle peak would be even more irrational. If these capex plans materialize, the industry could face a long-lasting supply glut;

3. Concerns about Intel and/or Samsung catching up to and/or surpassing TSMC in technological capabilities and gaining share of the leading-edge foundry market by offering a comparable or better value proposition to customers;

4. Concerns about the end of Moore’s Law and, hence, the long-term growth prospects of TSMC;

5. The fear of China invading Taiwan;

6. A lollapalooza/confluence of some or all of the above.

TSMC seems to have significant competitive advantages that could help it withstand cyclical downturns and competitive onslaughts. That said, a company’s value is convex in its cash flows’ growth rate, so there is a spectrum of growth rate possibilities that investors need to be comfortable underwriting.

A Chinese invasion of Taiwan seems to add more uncertainty than risk i.e. it is a danger whose probability and different outcomes cannot be reasonably assessed. Still, it is the event that is most likely to lead to a permanent loss of capital and even a total loss of capital in the darkest scenarios.

Before delving into each risk/uncertainty and TSMC’s competitive advantages, I’ll first explore:

1) Some background on the state and capital intensity of the semiconductor industry;

2) Some base rates to try to assess how realistic TSMC’s management’s forecasts are.

Semiconductor Capital Intensity/The End of Moore’s Law

Founded in the late 80s, TSMC pioneered the fabless-foundry model, enabling chip designers to launch companies without the onerous capital needs of semiconductor manufacturing. As fabless companies proliferated, then eventually consolidated through boom-and-bust inventory cycles in the industry, and companies with their own fabrication facilities reduced their manufacturing footprint or outright exited fabrication, TSMC grew in importance, manufacturing scale, revenue, and profits. Naturally, competition also emerged.

The semiconductor industry has been dictated by Intel co-founder Gordon Moore’s prediction (Moore’s Law) that the number of transistors per area of silicon and, hence, performance would double roughly every two years. Over the past 20 years, semiconductor revenues and silicon shipments have moved in lock-step, while transistor density, performance, and power efficiency have improved roughly as predicted by Moore’s Law. The increase in transistor density has meant that a consistent price/square inch of silicon translated to lower price/transistor, better performance/watt, or simply higher and more energy-efficient performance per dollar.

Exhibit 3: Industry revenues (in $m) and silicon shipments (in millions of square inches)

Source: SIA, Fabricated Knowledge

This rate of progress has been enabled by the rapid improvement in manufacturing tools and instruments. To make this improvement possible, wafer fabrication equipment (WFE) companies have had to tackle increasingly difficult physics problems. Hence, Moore’s Law’s progress has been predicated on increasing R&D investments on the part of WFE manufacturers, which, combined with the industry’s cyclicality, has been a spell for consolidation among WFE players. Today, the top 5 companies (Applied Materials, ASML, Lam Research, Tokyo Electron, and KLA) account for the bulk of WFE revenues and spent $9.3bn on R&D in 2021, about 1.7% of the entire semiconductor industry’s revenues. These companies have held the keys to improving performance and, hence, charge sufficiently high prices to earn great returns on these R&D investments.

The rising costs of manufacturing, coupled with the cyclicality of the industry, dissuaded a lot of the IDMs from participating in leading-edge manufacturing, and foundries picked up the capex tab but also claimed a larger piece of industry revenue to be compensated for their troubles.

Exhibit 4: Wafer Fabrication Equipment and foundry sales as % of total semiconductor revenue

Source: SIA, VLSI, Fabricated Knowledge

Exhibit 5: Total semiconductor industry, WFE, and foundry sales CAGR (nominal)

Thus, TSMC and its competitors have had to shoulder large and increasing capex burdens. As evident in the table above, to be economically viable, foundries have had to grow their revenues at a higher rate than the overall industry, though consistent profitability has proven elusive for most. As with most manufacturing, scale is critical, but, unlike many types of outsourced manufacturing, semiconductor fabrication is anything but commoditized. Few companies can afford to build leading-edge capacity at scale, and fewer can operate it economically (to be discussed later).

For the past 5 years or so, as improving transistor density has been approaching its physical limits, the rate of performance improvement has slowed below the rate predicted by Moore’s Law, and these slowing improvements have been increasing in cost. The higher equipment bills and the slowdown of transistor scaling have led to an increase in the cost per transistor at the leading-edge.

Exhibit 6: Transistor costs are rising (Gate costs can be used as a proxy for transistor costs)

Source: Fabricated Knowledge, Marvell 2020 Investor Day Presentation

There is further nuance to equipment costs – a significant amount (as much as 90% today according to TSMC) of tools used in one process node could in the past be reused in the next process node (lowering costs). Leading-edge foundries are also adding capacity (increasing costs), and every new node has required more processing steps, requiring more tools of newer and more expensive equipment to achieve the same throughput/capacity (increasing costs). On balance, each new node has proved more expensive for foundries.

Exhibit 7: Relative production costs by process node

Source: IC Knowledge LLC

Exhibit 8: My estimates of greenfield capex per 1,000 wafer starts per month of capacity

Source: TSMC, Applied Materials, SIA, Tokyo Electron, DigiTimes

The discussion of manufacturing costs has so far focused on the challenges and costs of fitting more transistors on a square millimeter of silicon and, hence, the front end of manufacturing. The back end, namely packaging, traditionally done by OSATs separate from foundries, has long been a performance bottleneck, perhaps overlooked because of the reliable performance improvement in accordance with Moore’s Law at the front end. At the risk of oversimplifying (see SemiAnalysis for a very informative intro), this limitation stems from the necessity of chips to communicate with other chips through metal interconnects and substrates, and the improvement in the density of those connection points has significantly lagged transistor scaling. The industry has turned to packaging for the next wave of performance improvement, as transistor scaling nears its physical limits. Large monolithic dies are very difficult to produce at leading-edge nodes (more on this later) and advanced packaging techniques have provided vital alternatives (chiplets used by AMD and Intel) in computing and also enabled revolutionary antenna technologies for 5G devices.

Historically a small sliver of WFE (typically <10%), back-end equipment is becoming an increasingly important corner of equipment industry. There are two pieces of good news for foundries: 1) packaging is becoming more tightly coupled with the front-end of manufacturing (e.g. this partnership) in which foundries specialize, and 2) advanced packaging could bring the next wave of performance improvement beyond Moore’s Law.

Exhibit 9: The next decade in manufacturing, according to a major advanced packaging equipment manufacturer

Source: ASML Investor Day, BE Semiconductor Hybrid Bonding presentation

The bad news is that its costs are incremental and not a substitute for front-end equipment.

Exhibit 10: Relative production costs by process node, front-end (FEOL) and back-end (BEOL)

Source: IC Knowledge LLC

The rising WFE bill has caused consolidation at the leading-edge after Globalfoundries bowed out of the race to 10nm. Today, only a handful of players are willing and able to pay the eye-watering equipment bills for production capacity at the leading-edge (and make it work): Intel, Samsung, and TSMC, with Intel struggling to catch up to Samsung and TSMC. Of these, TSMC is the only pure foundry and arguably (Samsung would argue) has the most advanced process in what it calls 5nm.

Exhibit 11: Share of non-memory wafer production by process node

Source: The Economist, VLSI Research

Exhibit 12: Top two companies’ spending as a % of total WFE sales

Source: Financial Times

The challenge that foundries are facing is delivering enough value to customers through silicon performance improvements at an acceptable yield (to be defined later) in order to charge wafer prices sufficient to earn an attractive return on the ever-increasing investments required at the leading-edge.

Some Base Rates

Considering how cyclical the semiconductor industry has been for its entire existence, it would be foolish to extrapolate its rapid growth of the past 18 months into the future, particularly when every player seems to be adding capacity to address shortages. This seems like classic pro-cyclical behavior that will inevitably end in a downturn. It would be more helpful to examine growth rates of the semiconductor industry and its relevant subsectors over longer periods of time, capturing full-length cycles. While the semiconductor industry is inextricably linked to global GDP, the industry’s rate of growth has accelerated and pulled away from global GDP in the past decade. The table below summarizes the growth trends of the semis and foundry industries and TSMC’s revenues over the past 20 years.

Exhibit 13: Nominal CAGRs for the industry

Source: World Bank, TSMC company filings, SEMI, WSTS

Within the semiconductor industry, logic semiconductor revenue has grown faster than the average in the past decade. Logic is now the largest segment in the semiconductor industry (tied with memory). Although TSMC offers analog and what it calls “specialty” technologies on lagging edge nodes, its business is almost entirely focused on producing logic integrated circuits or ICs (broadly digital processors such as CPUs). The company stopped disclosing the revenue between logic and other technologies, collectively referred to as “mixed-signal,” in 2015, when it was 75% logic and 25% mixed-signal. Despite the lack of disclosure, it’s almost certain logic is now an even larger chunk of revenue.

In short, TSMC’s growth is largely dependent on the growth of the logic IC market.

Transistor scaling is a major factor driving performance improvement in logic ICs, whereas others, such as analog ICs, are more reliant on design improvements. To be competitive, logic customers need to release new products with at least the same cadence and performance improvement as their rivals. Therefore, for their flagship products, they want to not only utilize the most advanced leading-edge process but also to make sure that they use the foundry supplier who has a reliable roadmap to the next most advanced leading-edge process. Each new iPhone’s processor (SoC), for example, is manufactured on TSMC’s most advanced leading-edge process node and has better transistor density and, hence, better performance than its predecessor. The same goes for Nvidia GPUs.

Referring back to the discussion of rising equipment costs, foundries are charging higher prices to recoup those costs. The most advanced leading-edge chips are also the ones with the highest performance, so the end products which they power are top-shelf. As a result, fabless companies’ foundry cost increases in each successive leading-edge node are largely passed on to their customers, as the end-product consumer demand is relatively inelastic. Therefore, these fabless customers’ growth is largely driven by chips fabricated on the most advanced leading-edge process. As a result, the logic industry’s growth is largely driven by the most advanced leading-edge process. The implication for logic foundries is fairly straightforward: the company with the most advanced leading-edge process reaps most of the industry’s growth.

TSMC’s growth in any given year has long been entirely driven by revenues from what were at the time leading-edge processes producing logic ICs, with lagging-edge processes typically declining year-on-year (2021 is a bit abnormal, with lagging edge growing). TSMC’s leading-edge revenues have accounted for more than half (between roughly half and two-thirds) of the company’s revenues. Management expects this proportion to increase this year. Since TSMC’s share of the foundry industry has exceeded 50% and has been growing since 2014, it follows that TSMC’s leading-edge growth has accounted for more than half of the foundry industry’s growth.

In conclusion, TSMC’s growth is not merely largely dependent on the growth of the logic IC market but also on its ability to maintain or extend its technology leadership.

The growth discrepancy between logic and the overall semiconductor market has widened over the past three years with logic growing at a 18.4% CAGR in the 2018-2021 period and total semis growing 5.8%. Notably, logic only declined 2.5% in the 2019 downturn, compared with the 12.7% of the entire industry.

TSMC has grown in step with the logic subsegment of the market in the period and managed to grow 2019 revenues 3.7%. What is noteworthy about this 3-year period is that it is during this period that TSMC started pulling away from Intel and, to a lesser degree Samsung, in terms of process node capability.

Proof of TSMC’s manufacturing superiority can be found in the fortunes of two of its largest customers, AMD and Qualcomm, with the former gaining consumer and server CPU share from Intel with its TSMC-manufactured CPUs and the latter winning the SoC socket in Samsung’s latest flagship Galaxy phone with its newest Snapdragon chip from Samsung’s own Exynos. Rumor has it that Qualcomm will be manufacturing the Snapdragon chip at TSMC, moving from Samsung’s own foundry services (Qualcomm uses both Samsung’s and TSMC’s foundry services). AMD moved from its leading-edge production to TSMC from its long-standing partner Globalfoundries in 2018, after Globalfoundries decided to give up the leading-edge race. It has since gained significant x86 CPU market share in every CPU subsegment, including in the most lucrative and fastest growing server market, at Intel’s expense.

Exhibit 14: AMD’s CPU market share

Source: Tom’s Hardware, Mercury Research

Finally, the rumored negotiations between Intel and TSMC for Intel to secure capacity at TSMC for its GPU chiplets are a testament to TSMC’s lead. These rumors seem to be substantiated by this bit in Intel’s latest 10-K:

Strategic use of foundry capacity. We expect to expand our use of third-party foundry manufacturing capacity, which will provide us with increased flexibility and scale to optimize our product roadmaps for cost, performance, schedule, and supply. Our use of foundry capacity will include manufacturing for a range of modular tiles on advanced process technologies.

Back to base rates, in justifying their 15-20% CAGR forecasts for “the next several years,” TSMC’s management have repeatedly referred to “industry megatrends,” namely 5G, AI, and high-performance computing (HPC), which, with some exceptions in 5G radio, are predominantly leading-edge logic applications.

So, to achieve its forecasted growth through 2025, TSMC needs to at least either:

1) maintain its share in the logic market, and the logic market would need to achieve roughly the same 3-year CAGR as the 2018-2021 period, a rate above its 5-year or 10-year CAGR;

2) gain share in logic if logic’s 3-year CAGR slows to closer to its 5-year or 10-year CAGR;

3) concede some share in logic, whose growth would need to accelerate from its growth rate the past 3 years.

If the industry’s historical growth rates are any guide (huge if given various secular developments), an acceleration in the logic market’s growth seems least likely. This leaves TSMC with one option: maintain or extend its technological leadership and other competitive advantages.

But this is not the whole story – the three major logic foundries, TSMC, Intel, and Samsung are planning to add huge amounts of capacity (see Exhibit 22 and the following discussion), and most of that incremental capacity will be leading-edge. Per Intel’s CEO, Intel will not be a major foundry player until 2025 as developing world-class foundry services and onboarding customers at scale is a long and difficult process. Until then, Intel will be a competitive threat in logic mostly through their rivalry TSMC’s customers, with whom Intel will strive to compete mostly with internally-manufactured chips. Samsung already has developed foundry services and foundry relationships with customers such as Nvidia and Qualcomm, but these customers mostly use Samsung just to have a second source and most of the volume and the most advanced chips go through TSMC. This could change as Samsung adds capacity, but Samsung needs to first catch up in process technology.

Of course, TSMC’s future beyond 2025 is of vital importance to any investment thesis. In addition to meeting its forecasts in the next few years, TSMC needs to have a bright future ahead beyond 2025. Considering the huge capacity that will be available to logic customers beyond 2025, that bright future will be conditioned, again, on TSMC’s ability to maintain or extend its technological leadership and other competitive advantages.

I don’t know the exact price and unit breakdown, but in light of capacity shortages, it is safe to assume that price increases have been a big contributing factor to the foundry industry's revenue growth from logic. As a sanity check, silicon area shipments of the entire semis industry grew 20% over the past two years, while $/square inch of silicon grew 13%. In TSMC's case, wafer ASPs rose 19%, while wafer shipments grew 41% in the past two years.

While growth in the industry is mostly driven by the most advanced-leading edge process, there is still a large part of the industry that is using older technology. Remember, TSMC’s leading-edge (currently 7nm and below), though rising in proportion, is only half of the company’s revenue. Logic fabless customers want the most advanced process and a roadmap for their flagship products, but are content with older technology for the rest of their portfolio.

Even if there is sufficient demand to drive high logic wafer unit growth, if that growth meaningfully lags capacity growth, pricing will suffer and weigh on total logic foundry revenues, especially on slightly older processes, which are still a large slice of TSMC’s revenue.

A final note before diving into TSMC’s competitive advantages – base rates are a good sanity check but don’t tell us much about the future. However, as noted earlier, TSMC’s management have significantly more information than anyone else in the industry and are certainly well aware of these base rates and its competitors’ capacity plans. They rarely make such long-term forecasts and stress they do not build speculative capacity. They might have a better handle on the direction of the industry than most, but they do not have a crystal ball. What they can focus on are the company’s competitive advantages.

I’ll now discuss these competitive advantages in Hamilton Helmer’s “Power” framework (with a nod to Nick Sleep).

TSMC’s Competitive Advantage #1: Scale Economics (Shared)

TSMC is not maximizing short-term profits. Articles about TSMC’s 20% in wafer prices often fail to mention the costs involved in building out capacity for these wafers. One could argue that TSMC earned the right to extract huge value from its customers, since TSMC put a lot of capital at risk to push the envelope of leading-edge manufacturing and build out capacity, but that would be inconsistent with TSMC’s business philosophy. The company’s management has taken a different path. They refer to customers as partners and explain their pricing decisions as “strategic, not opportunistic.” Management has long realized the value of co-developing processes with customers and that such collaboration and opportunistic pricing are not congruent.

This is clear from a quick look at TSMC’s financial statements – RoIC has been relatively stable over the past 20 years, even as the company has become the clear leader at the leading-edge. The benefits from TSMC’s superior processes and economies of scale are shared with customers to assure an industry-leading value proposition. Needless to say, this pricing is a significant barrier to entry and competitive advantage.

The years of slightly higher returns preceded periods of substantial investments, so the profits made in those higher return periods were used to finance the increased capital expenditures (TSMC has maintained net cash positions for at least the past 20 years). This has been well understood by leading-edge customers, such as Apple, for whom an industry-leading technology roadmap, supported by sufficient capacity, is a key aspect of suppliers’ value proposition.

Apple, for example, does not have an alternative to TSMC at 7nm and below. Apple initially left Samsung because Samsung is its major competitor and was tempted to take a peek at its IP. This dynamic is perhaps extant today but is no longer the reason Apple has stayed with TSMC as its sole manufacturer of the A-series processors. Samsung could arguably no longer provide the same performance at the leading-edge, does not have sufficient capacity for external customers, and lacks the packaging processes Apple co-developed with TSMC. TSMC could charge Apple a lot more than $17-20k per wafer (these $ASPs circulate online and sound plausible) at 5nm… at least for a few years before Apple and other disgruntled customers help Intel and Samsung catch up to TSMC.

A deeper look into the customer relationship with Apple would serve well to illustrate the value TSMC offers to its customers, derived from its shared scale economics strategy.

Apple is usually the first customer of TSMC’s latest process node. TSMC sent hundreds of engineers to Cupertino in 2013 to work with Apple on its transition from Samsung’s foundry services. This close collaboration has continued ever since, and Apple is an important contributor to key parts of the technology development. Apple has a very big incentive to make these contributions, considering the leading-edge capex requirements discussed earlier – it simply wouldn’t be feasible for Apple to go completely vertical and manufacture its own chips, unless it’s prepared to lose money in the endeavor.

Here’s why.

Assuming one knows the die size of an A-series processor, the iPhones’ (and now Macs’) workhorse processor, the process node on which it is manufactured, and the die’s yield, one can make enough estimates to illuminate the economics faced by TSMC and Apple and, therefore, to assess who gets what value in the relationship. These estimates, however, rely on a number of assumptions and so are only as good as those assumptions, but hopefully the logic behind both assumptions and estimate calculations is sound.

Let’s take the A14 and A15 processors of the iPhone 12 and 13 series, respectively, which are both manufactured on TSMC’s 5nm process. Some data presented at TSMC's 2021 Tech Symposium on its 5nm defect rate/cm^2 , which is a key component in yield calculations (to be discussed in more detail later), reveals that 5nm initial defect rates at high volume manufacturing were actually better than 7nm ones, and the rate of yield improvement was comparable, so TSMC probably achieved better initial yields on the A15 processor, despite its larger die size. Net, TSMC probably managed to squeeze more A14s out of a wafer on the 5nm process due to the smaller die size.

Demand for the latest iPhone is seasonal and fleeting, but TSMC needs to build enough capacity to satisfy that peak demand. Here comes a key part of the TSMC-Apple relationship. Estimates of unit sales of the iPhone 13 (not mine) suggest it has been selling better than the iPhone 12 in the holiday season. It appears Apple shipped about 60m iPhone 12 units in 4Q20, which I assume means TSMC had had to build peak capacity for 40 million SoCs (pre-building some inventory). Assuming Apple shipped around 80 million iPhone 13 units in calendar 4Q21, TSMC probably needs to have built peak capacity for 65 million phones. Apple does not release unit shipment numbers and I don’t know what the build cycle looks like, but this is for illustration purposes only. It’s evident from earnings calls that peak capacity planning is top of mind for management, and I’ll discuss the reason shortly.

Exhibit 15: My estimates of A14 and A15 peak capacity needs; assumptions are in orange

Source: AnandTech, TSMC, Omdia

The illustrative table above suggests that TSMC must have increased capacity by almost 90% for the iPhone 13, but since iPhone sales are seasonal and dominated by the newest models in the quarters of and following their release, the iPhone 12 would require significantly less than peak capacity after iPhone 13’s release. Assuming that after 2022 the iPhones 12 and 13 decrease in volume at a rate similar to that of the iPhone 11, one can estimate wafer demand in the next 5 years, which is the period that TSMC uses as the equipment’s useful life in accounting for depreciation.

Then, using the capex/1,000 wafer starts per month (kwpm), one can estimate how much TSMC must spend to build out this capacity. TSMC plans to spend about $400m/kwpm to build out its 5nm fab in Arizona. However, the Arizona fab buildout will be starting from scratch (greenfield). TSMC’s 5nm capacity in Taiwan uses a lot of existing infrastructure, as well as a significant amount of 7nm tools (about 90% of tools can be repurposed, per TSMC’s comments). EUV is a larger part of the 5nm process, so there is still a significant incremental investment. I assume $200-$250m/kwpm. Finally, using TSMC’s disclosure, one can estimate labor costs and variable costs/wafer. The results are summarized in the table below.

Exhibit 16: Illustration of TSMC’s iPhone 12 and 13 economics excluding opex; assumptions are in orange

Source: TSMC, IC Knowledge LLC

This analysis is for illustrative purposes only, and all corrections are welcome. It aims to illustrate that TSMC takes on the huge costs of building out sufficient capacity for Apple, who only use the full capacity for no more than two quarters. The result is that TSMC will be burning a significant amount of cash (and this is before considering opex) unless it finds enough customer demand to fill the capacity after satisfying Apple’s peak demand. Any miscalculation in peak capacity planning costs dearly. Foundries live and die by yield and utilization, and how utilization impacts per wafer economics is illustrated below (opex excluded from cost assumptions and estimates).

Exhibit 17: Illustration of wafer unit economics, excludes opex

Source: Derived from TSMC company filings

With each new node, it appears TSMC sets a new record for the number of customers it has secured on the node. Initial designs (tape-outs) for the 3nm exceed those for 5nm. These customers’ products also target an increasingly diverse set of applications and end-markets – from smartphone processors and notebook CPUs to specialized AI chips designed by start-ups and hyperscalers and crypto mining data center processors. Thus, wafer demand volatility is smoothed out to an extent. The company also has a large and highly cash-generative base of older generation processes. For instance, the 90nm process was introduced in 2004 and in generated almost NT$35bn ($1.2bn) of revenues in 2021, using equipment that has long been fully depreciated for accounting purposes and has required negligible maintenance capex for more than a decade. Many of the logic designs produced on older processes will eventually move down to 5nm.

All this allows TSMC to plan accordingly and set wafer prices at levels that offer such value to each customer that it makes it really hard to think of how a rival can compete. Using the data presented above, I estimate that Apple pays ~$40-50 per chip for A15, which powers a phone whose (rumored) bill of materials is ~$500 and is selling for >$1,000 – scale economics shared at work.

Competitive Advantage #2: Process Power/Superior Technology

I discussed one of the two major operational factors dictating a fab’s profitability, namely utilization. The other one is yield. Fitting square chips on a circular wafer means that a portion of the wafer is lost at the edges. Additionally, each step of the manufacturing process faces some probability that a defect occurs somewhere on the wafer. A defect renders the chip on which it occurred (at least partially) useless. The wafer’s yield is the percentage of the wafer area that is defect-free. The yield of a chip (or die) is the number of defect-free (good) chips as a percentage of the maximum number of chips that can theoretically fit on a defect-free wafer. A larger die size means fewer chips can be fit on a wafer, so one defective chip represents a larger percentage loss (compared to a smaller chip). Hence, chip yield and chip die size are inversely related for a given defect rate.

Exhibit 18: Basic die yield equation

Source: From the book Extending Moore’s Law through Advanced Semiconductor Design and Techniques

Wafer purchase agreements between foundries and their customers are confidential and differ from customer to customer, but all customers are in the business of selling or using non-defective chips, so these agreements usually stipulate a minimum acceptable yield. If the foundry fails to deliver, it has to make the customer whole through either monetary compensation or extra wafers. In effect, the customer wants to guarantee the delivery of a certain number of chips for its money (price/chip). Volume discounts are also features of the typical wafer purchase agreement.

The basics of yield economics are summarized by the equation below. It simply formalizes the fact that a foundry will have to process more wafers to deliver the same number of chips and earn the same revenue as a foundry achieving better yield.

Exhibit 19: Basic relationship between wafer cost and die yield

Source: From the book Extending Moore’s Law through Advanced Semiconductor Design and Techniques

Of the variables in the basic yield equation, the one that’s within a foundry’s control is the defect rate. Minimizing defect rates has a learning curve for each node, and since the majority of tools used in a given node can be repurposed for the next node, the learnings cumulate across nodes. What is more, as precise as the tools are, manufacturing is a probabilistic rather than deterministic, and, in the age of AI, foundries are increasingly gathering and analyzing data to improve the learning curve. Hamilton Helmer would term this hysteresis:

“[the] process advances are difficult to replicate, and can only be achieved over a long time period of sustained evolutionary advance.”

Not only is leading-edge yield a product of hysteresis, but the difficulty of achieving it at every node is growing exponentially. Referring back to the die yield equation, die yield is decreased by each additional critical mask layer (through a power law), and each mask layer requires several processing steps. The figure below illustrates the rise in the number of processing steps at leading-edge nodes. Whether the defect rate at each processing step is probabilistically dependent on or independent of other steps, each step entails some probability of a defect occurring. To achieve yields of 90% at 5nm, a foundry must execute more than 1,000 incredibly sophisticated processing steps nearly perfectly, and this is exactly what TSMC does. For example, to achieve 90% yield at volume with 1,000 processing steps, the failure rate of each step must be 0.01% (assuming all 1,000 steps are probabilistically independent events).

Exhibit 20: Number of process steps per wafer at the leading-edge

Source: Fabricated Knowledge, CMC Materials Investor Day

What’s even more impressive and terrifying for competitors is that the accumulation of manufacturing expertise in one node often helps achieve better yields on the next one. The learning curve for TSMC’s 7nm and 5nm processes is illustrated below.

Exhibit 21: TSMC’s 7nm and 5nm defect rate progression

Source: TSMC’s 2021 Tech Symposium

Advanced packaging is not a substitute for front-end complexity at the leading-edge but rather layers on additional complexity. Manufacturing smaller leading-edge chips (chiplets) to package together might improve individual die yields and costs, but packaging the chiplets also has a yield of less than 100%. For sophisticated computing chips with large die sizes near the reticle limit, large monolithic chips might not be feasible at all, so advanced packaging of chiplets might be the only solution. In effect, advanced packaging raises the yield hurdle and adds additional steps lengthening wafer lead-times.

Advanced packaging is analogical to the leading-edge in the back-end, and it has its own engineering challenges, more mechanical than chemical/optical when compared with the front-end. TSMC is well on its hysteresis path in advanced packaging as well after pioneering fan-out packaging (InFO) in high volume with Apple back in 2016.

Finally, there is the issue of cycle times or throughput. RoIC is the product of asset turnover and operating margin, and wafer capacity is similarly a product of throughput and yield. Therefore, the return on the huge equipment investments discussed earlier is a function of both yield (non-defective chips/wafer) and throughput (wafers processed/unit of time).

A semiconductor fab is a collection of numerous tools from various vendors. Each tool has a maximum theoretical throughput, and it’s the foundry’s job to get as close to that throughput within a certain defect rate envelope. Processing times per mask layer vary between foundries, and the best foundries take 20-50% less time than average or below-average foundries. These time savings really add up at the leading-edge with the large number of steps involved.

However, according to ASML, the biggest contributor to cycle times is the wait times between steps. Wait times also tend to increase with fab utilization. Consequently, process flow automation and optimization can be real differentiators in productivity and cost. These, like front-end and back-end defect rate optimization, are also the result of years of accumulation of expertise or hysteresis.

Competitive Advantage #3: Counter-positioning/Revolutionary Business Model

This one is fairly straightforward and well-understood but is hugely important and so merits a brief discussion. As the world's first pure-play foundry, TSMC had a unique proposition when it was founded in 1987 - we will only manufacture the chips you design and will not compete with you by designing and manufacturing our own chips. The Apple-Samsung IP incident reveals how important this is for protecting IP. Nvidia and AMD, Intel’s major fabless competitors, are two of TSMC’s customers who begin using TSMC’s most advanced process not long after Apple. I would have thought them to be two of Intel’s most unlikely foundry customers, primarily because of the issue of IP protection, Intel’s assurances that the foundry business will be a walled-off entity separate from Intel’s own chip business notwithstanding. But then Jensen Huang, Nvidia’s founder and CEO, seemingly refuted those concerns at a recent Q&A session (emphasis mine):

Our strategy is to expand our supply base with diversity and redundancy at every single layer. At the chip layer, at the substrate layer, at the assembly layer, at the system layer, at every single layer. We’ve diversified the number of nodes, the number of foundries. Intel is an excellent partner of ours. We qualify their CPUs for all of our accelerated computing platforms.

[…] Our engineers work very closely together. They’re interested in us using their foundries. We’re interested in exploring that. […] we’ve been working closely with Intel, sharing with them our road map long before we share it with the public, for years. Intel has known our secrets for years. AMD has known our secrets for years. We’re sophisticated and mature enough to realize that we have to collaborate. We work closely with Broadcom, with Marvell, with Analog Devices. TI is a great partner. We work closely with everybody and we share early road maps. Micron and Samsung. The list goes on. Of course, this happens under confidentiality. We have selective channels of communications. But the industry has learned how to work that way. […] We’re quite comfortable with our confidence in what we do. We’re very comfortable working with collaborators, including Intel and others. We’ve overcome that – it turns out that paranoia is just paranoia. There’s nothing to be paranoid about. It turns out that people want to win, but nobody is trying to get you. We try to take the not-paranoid approach in our work with partners. We try to rely on them, let them know we rely on them, trust them, let them know we trust them, and so far, it’s served us well.

Perhaps Jensen’s comments should be taken at face value, perhaps they are part of some sophisticated PR campaign. The logical thing to do would be to take them at face value to avoid underestimating the risk posed by Intel’s foundry services.

If the IP protection issue is no longer an issue at all for either Intel or Samsung, it might seem that there would be no obstacles to Intel’s and Samsung’s competitors using their foundry services. In fact, the addition of more leading-edge capacity would be most welcome to diversify the supply chain. But then there are the issues of capacity prioritization and purely strategic considerations. The pandemic drove huge demand for both consumer and server CPUs. Would AMD trust Intel Foundry Services to honor its wafer obligations when Intel’s internal production capacity is running full, and the mothership is missing out on the unforeseen revenue windfall? Would Intel want to include adjustable wafer prices in the wafer purchase agreements to be compensated in such events, and why would AMD sign such a contract? The same logic broadly applies to Samsung and its chip competitors as well. Conversely, in less auspicious times, when Intel is struggling to fill its capacity for internal use, fab customers would be coming to the rescue. From a strategic point of view, helping your major competitor’s utilization of very expensive capacity, especially during a cyclical downturn doesn’t seem ideal.

And if Intel and Samsung are unable to attract at least some of their competitors as customers, how would they enlist enough customers and secure enough demand to make the peak capacity economics discussed above work? And if they can’t make the economics work, how can they offer low enough prices to have a better or at least comparable value proposition compared with TSMC’s and so forth.

Jensen’s comments were not all bad news for TSMC. In fact, they were quite complimentary:

To be in a foundry at the caliber of TSMC is not for the faint of heart. This is a change not just in process technology and investment of capital, but a change in culture, from a product-oriented company, a technology-oriented company, to a product, technology, and service-oriented company. And that’s not service as in bringing you a cup of coffee, but service as in really mimicking and dancing with your operations. TSMC dances with the operations of 300 companies worldwide.

Our own operation is quite an orchestra, and yet they dance with us. And then there’s another orchestra they dance with. The ability to dance with all these different operations teams, supply chain teams, it’s not for the faint of heart. TSMC does it just beautifully. It’s management. It’s culture. It’s core values. They do that on top of technology and products.

[…] With respect to Intel, the foundry discussions take a long time. It’s not just about desire. We have to align technology. The business models have to be aligned. The capacity has to be aligned. The operations process and the nature of the two companies have to be aligned. It takes a fair amount of time. It takes a lot of deep discussion. We’re not buying milk here. This is about integration of supply chain and so on. Our partnerships with TSMC and Samsung in the last several years, they took years to build. We’re very open-minded to considering Intel and we’re delighted by the efforts that they’re making.

In addition to the technology capability, there is a huge services capability that Intel and Samsung need to mimic to successfully compete with TSMC. Intel has openly admitted that the need to bring foundry services capabilities into the organization was a major consideration in the Tower acquisition and was most probably a big reason behind the attempt to acquire Globalfoundries. Services are by definition labor intensive, and TSMC has admitted that sourcing human capital is a serious concern for the business. The point is that the burden of proof lies on the shoulders of the new entrants rather than the incumbent.

Competitive Advantage #4: Network Effects

Network effects are usually associated with Internet platforms, but, effectively an aggregator of leading-edge demand, TSMC benefits from them, too. “Network effects” simply means the value of a product or service to each customer increases with the number of customers using it. There are several network effects in TSMC’s foundry services. First, the wafer economics described in the shared scale economics section are made possible by the number of customers whose orders fill the newest node capacity built for peak Apple demand.

Network effects also exist in the sophisticated IP ecosystem which TSMC built over the past ~15 years. Once the initial design is complete, every chip design needs to be qualified for production, and that process’ complexity increased with the advance of Moore’s Law. To speed the process up, TSMC launched the Open Innovation Platform (OIP) in 2008. Essentially, it was a library of design kits, IP blocks, and other design tools, which TSMC had qualified for its design rules.

Shortly thereafter, it also launched its CyberShuttle service (which it copied from a US academic idea). It was the industry’s first multi-project wafer service – companies would send their mask designs to TSMC, and TSMC would use them to produce many different chip designs on the same wafer, cut the chips up, and send them back to the customers for verification; this would greatly reduce mask design costs as compared to having each company using separate wafers with their own masks for their prototypes.

CyberShuttle directly reduced design costs, while OIP reduced time-to-market, which is a real economic cost for customers.

Both of these initiatives were copied by competitors, but TSMC had the first-mover advantage. Design software tools companies like Cadence and Synopsys and IP companies like ARM had the incentive to work with TSMC to have their tools and IP qualified for TSMC’s processes, given its large customer base, and new customers or existing customers expanding product lines chose TSMC for the lower design costs and short time to market, and so the cycle went. TSMC is today at the center of an ecosystem of IP companies, design tools makers, front-end and test and packaging equipment suppliers, and fabless companies. As a result, it has the broadest IP library and years of learning and co-development of various chips.

Before TSMC’s business model disrupted the semiconductor industry, IDMs were mostly manufacturing proprietary chips (they did have some foundry services), so they developed expertise in the manufacturing of the types of chips in which they specialized. TSMC opened its doors to all companies and so produced chips with various architectures and die sizes for a diverse set of applications. Again, this was copied as competitor fabs emerged, but TSMC again had the first-mover advantage. This exposure probably helped TSMC with establishing its most important competitive advantage (together with its shared scale economics pricing philosophy) – its ability to achieve economically viable yields on industry-leading technology processes.

Risks

After discussing TSMC’s competitive advantages, it’s time to address what I think are the market’s major concerns.

• Concerns about the strength of future semiconductor demand – how much of the current demand is “real” rather than mere inventory build-up and, hence, when would an inventory glut appear and how severe would it be;

Per 1Q22 earnings calls, it seems that every semiconductor and WFE company is of the view that the shortages would last at least through this year. Those with internal production are racing to add capacity and to try to secure more capacity from foundries, while their customers are trying to build up inventory (so far mostly unsuccessfully). It seems almost inevitable that a big inventory correction is due. With the exception of the recovery from the Dotcom Bubble, every period of similar growth as experienced over the past 18 months was followed by a correction, most recently in 2019. Only the most skillful/lucky are capable of timing the next correction, however, and the timing shouldn’t matter for a long-term investor in theory – 3 years of 15% growth in each or an annual 10% contraction followed by 35% and 25% growth both get you to a 15% CAGR, but the latter ride could be quite painful to endure.

Under a more worrisome scenario, the inventory correction is deeper than anything in recent memory and is, in fact a symptom of something more grievous, leading us to…

• Concerns about the plans of enormous supply capacity additions that could create a long-lasting supply glut.

In a recent interview, legendary investor Gavin Baker had this to say about the semiconductor industry:

Generally, I’m negative on semiconductors on a short-term basis. Nassim Nicholas Taleb said it best: “I’ve seen gluts not followed by shortages, but I’ve never seen a shortage not followed by a glut.” We haven’t seen a true semiconductor capacity cycle in more than twenty years. The last time you had this kind of ramp in semiconductor capital expenditures, their stocks imploded. It was not until 2015, that semiconductor wafer fab equipment spending reached its 2000 peak. What’s more, government subsidies like the Chips Act are geopolitically very important for America and Europe. But by definition, when supply in any industry goes up for geopolitical rather than economic reasons, it’s very negative for the supply and demand balance in that industry.

Capacity addition announcements are ubiquitous across the semiconductor industry but leading-edge foundry ones are most pronounced and most consequential for TSMC. TSMC is the capacity leader in 200mm wafers as well (with a ~10% share), but its 200mm fabs accounted for perhaps 7% or less of 2021 revenue. SEMI expects the industry to grow 200mm capacity by 21% in the next two years, which would be massive, considering 200mm capacity has declined over the past 5 years. But this pales in comparison to leading-edge capacity expansion announcements from Intel, Samsung, and TSMC.

Exhibit 22: Intel’s, Samsung’s, and TSMC’s capex plans

Source: Company commentary

At their 2022 Investor Meeting, Intel’s management announced plans to invest ~$150bn in capex through 2026 as part of their foundry ambitions. In 4Q21, Samsung announced plans to triple capacity in the company’s LSI and Foundry divisions through 2026, after previously announcing plans to invest $150bn in the segments through 2030. With some assumptions around the cost of 1kwpm capacity at the leading-edge and the cadence of Samsung’s capex spending, one can roughly estimate the leading-edge capacity coming online in the next 5 years as implied by these capex announcements.

The numbers are staggering – the calculations in Exhibit 22 suggest ~14.5 million leading-edge 300mm wafers of annual capacity could be installed during the period. For context, TSMC’s FY21 total (including lagging edge) annual wafer capacity was 13-14 million 300mm wafer equivalents. Not all, but most, of this capex will be for incremental capacity, but maintenance capex will be significantly lower than depreciation, due to tool reuse, the cadence of migration to the most advanced leading-edge node, and the industry quirk of running fully depreciated fabs for long periods of time beyond their useful life. Net, the total capex number is huge.

Not all of the capex will be dedicated to leading-edge capacity, but the cost of lagging-edge capacity is significantly lower, which means more wafers added per dollar spent.

The estimates above are subject to many assumptions and could easily be flawed, but here’s a simpler way too frame the numbers: in the next three years, the three giants are planning to spend close to $270bn (subject to assumptions about Samsung’s spending cadence), compared with $146bn spent over the past three years by the entire foundry and logic IDM industries.

How much of these plans are real and how much are political posturing to secure government subsidies and preferential treatment is difficult to assess. Even if they are all real, Intel’s foundry revenue plans reveal that translating this expenditure into revenue is quite slow, particularly for greenfield investments (which will account for a significant portion of these investments) – Intel’s CEO Pat Gelsinger said at the Investor Meeting that onboarding new customers to leading-edge processes is a 3-year process, and that the foundry business is really a FY25 and beyond opportunity. The company expects FY23 foundry revenues of ~$1.5bn, from $900m in FY21.

Still, should these capex numbers materialize, I suspect there could be a significant risk of overcapacity in the industry beyond 2025. The effect this supply glut will have on TSMC will depend on whether it maintains its technological leadership. Half of its 2021 revenue was derived from 7nm and 5nm processes and associated advanced packaging, technologies over which TSMC has a near monopoly. This proportion will almost certainly increase this year and, given the number of 3nm tape-outs, could very likely rise further in 2023. The bulk of TSMC’s revenue will most probably continue to from the most advanced leading-edge processes. This revenue will be immune to supply gluts if the company is the only game in town, but the remainder will certainly suffer.

• Concerns about Intel and/or Samsung catching up to and/or surpassing TSMC in technological capabilities and gaining share of the leading-edge foundry market by offering a better value proposition to customers;

Though TSMC spent $4.5bn on R&D in 2021 (about half of the combined R&D budget of the top 5 WFE companies) and ranks fourth among all US patentees, some of its most valuable IP is the product of years of learning from experience and data accumulation and cannot be found on the balance sheet. But it is an asset that enables TSMC’s leadership. While a lot of the R&D burden is shared with customers who make significant contributions to the development of new processes, TSMC’s manufacturing expertise is a very opaque IP asset that is next to impossible to reverse-engineer.

Intel and Samsung are leading-edge powerhouses, as well, but TSMC is a few steps ahead, and that advantage is difficult to surmount in a hysteresis-driven process. Indeed, TSMC surpassed Intel, but it took a few years after Intel made the fateful decision not to use EUV (it has since reversed course). It is possible that TSMC makes a similar mistake in the future, but it also might be that customers have the incentive to help steer its technology roadmap in the right direction not only because they face not insignificant switching costs, but also because these customers might be reluctant to use the foundry services of competitors, as discussed earlier.

It might be overly simplistic, but the fact that AMD’s and Intel’s gross margins are converging, while AMD is beating Intel on price and paying TSMC significant gross margin (though probably below the corporate average) while Intel is still at least a node behind seems to point to TSMC’s superior yield at the leading-edge. I might be completely off on this, so, again, corrections are more than welcome.

Exhibit 23: Intel’s and AMD’s gross margins

Source: TIKR

Beyond yield, there are other economic obstacles to Intel offering competitive pricing without decimating its margins – in a recent interview, TSMC founder Morris Chang said this:

There’s a lack of manufacturing talents to begin with. I don’t really think it’s a bad thing for the United States, actually, but it’s a bad thing for trying to do semiconductor manufacturing in the U.S. We have actually had a manufacturing plant in Oregon for 25 years—and 25 years, that’s a long time. And we send all kinds of people, we change the managers, change the engineers, we use both America, local engineers, we also send engineers from Taiwan to Oregon to try to improve the performance. But improvement in its performance has happened. However, the cost difference between Taiwan manufacturing and Oregon manufacturing has remained about the same. The same product, the Oregon cost, is about 50 percent more than the Taiwan cost. Well, of course for us, the Oregon product is still profitable, although not nearly as profitable as the Taiwan product. So still we have maintained it. We started it in 1997. Initially it was chaos, it was just a series of ugly surprises because when we first went in, we really expected the costs to be comparable to Taiwan. And that was extremely naive. But after a few years of trying to make it work, we had to settle down, we had to accept it. And since it was still profitable, of course, we still accepted it, but we didn’t expand it. That was Oregon. We still have about a thousand workers in that factory, and that factory, they cost us about 50 percent more than Taiwan costs.

Now, Arizona: that will be a bigger scale venture, a bigger scale manufacturing than the one in Oregon, much more advanced technology, et cetera. And of course, we did it at the urging of the U.S. government, and we felt that we should do it. Basically, I was already retired at that time the decision was made. So, the decision was made by the current chairman. But anyway, we think that the recent effort of the U.S. to increase onshore manufacturing of semiconductors, right now you’re talking about spending only tens of billions of dollars of money of subsidy. Well, it’s not going to be enough. I think it will be a very expensive exercise in futility. The U.S. will increase onshore manufacturing of semiconductors somewhat. But all of that will be very high-cost increase, high unit cost. It will be noncompetitive in the world markets where you compete with factories like TSMC.

Samsung and Intel in particular will have to not only catch up TSMC in terms of achieving satisfactory yields on the most advanced leading-edge process at volume production but also do so cheaply enough to offer competitive pricing to their foundry customers.

Of course, Morris Chang might be biased and has not been on the ground for several years (he retired in June, 2018), but he is also probably the best and most experienced foundry manager out there. In response to the interview, analysts at Digits To Dollar argued that the Taiwan dollar has been manipulated versus the dollar (to about 50% too cheap) to maintain Taiwan’s competitiveness. The weakness of the Taiwan dollar would mostly benefit TSMC in its labor costs, as its capex and a large portion of wafer materials costs are sourced from American, European, and Japanese companies. I estimate labor accounts for about 4% of fixed costs/kwpm. I suspect the scale and efficiency of TSMC’s fab infrastructure in its large Taiwanese industrial complexes (which is responsible for its high wafer throughput) is a bigger contributor to TSMC’s cost advantage. The company has been perfecting its fab automation for years to the point where its labor efficiency is world-class:

Exhibit 24: TSMC’s 2021 revenues/employee compared to other high-return manufacturing and asset-light businesses

Source: Company filings

Semiconductor fabrication needs huge amounts of electricity and water, so these are significant portions of variable per wafer costs. Government subsidies and/or better infrastructure and access to those as compared with the island of Taiwan where most of TSMC’s facilities are could alleviate the burden of those costs for Intel and Samsung. However, TSMC also enjoys preferential government treatment and has huge infrastructure in place that probably enjoys some economies of scale.

Russia’s war on Ukraine united the West, and aggravated geopolitical fears around the concentration of power in such crucial industries as energy away from home. The newfound political will to support key areas of the private sector might eventually tilt the economics in Intel’s and Samsung’s favor.

It's unwise to dismiss Intel’s and Samsung’s ability to catch up to or even leap ahead of TSMC in technological capabilities. Despite the conflicts of interest, customers are typically uneasy about supplier concentration, and the pandemic-induced supply chain disruptions probably heightened that unease. It’s likely that they will collaborate with Intel and Samsung to bring them up to speed, just to have an alternative to TSMC. However, this argument cuts both ways, and fabless companies will probably continue to prefer TSMC, by virtue of its business model. This battle is TSMC’s to lose.

Ultimately, neither the technological capabilities of Intel and Samsung, nor the power of government sticks and carrots are to be underestimated, and the combination of the two might help Intel or Samsung topple TSMC beyond 2025.

On the China front, domestic foundries’ capabilities are nowhere near Intel’s or Samsung’s. China’s national foundry champion, SMIC, is living proof that simply throwing money at the problem of achieving economically-feasible yields at the leading-edge is no solution. SMIC is many years behind Intel, Samsung, and TSMC, despite the seemingly endless subsidies, government incentives, and the constant influx and exodus of elite managers, including alleged trade secret thieves from TSMC and Samsung. The US embargo on EUV tools won’t exactly help China’s cause either. The government support for domestic foundries in China is definitely stronger than in the West, but that’s a necessary but not sufficient condition for Chinese foundries to topple TSMC in the near future. The long-term risk of credible Chinese competition, however, is definitely not to be overlooked when thinking about TSMC’s position beyond “the next several years.”

• Concerns about the end of Moore’s Law and, hence, the long-term growth prospects of TSMC

Transistor density is nearing the ceiling imposed by laws of nature, and even the biggest Moore’s Law optimists, such as ASML, see transistor scaling continuing through the end of this decade but recognize that its pace will slow and it will be one of several contributors to performance improvement. Advanced packaging (systems scaling), new materials, and new IC designs/architectures will be the other contributors. TSMC already has a significant advanced packaging business and surely exploring all promising new technologies, but whether the company will be able to establish itself as the leader in delivering performance/dollar gains year after year in the new paradigm, whatever it might be, is difficult to assess.

TSMC has gained the trust of the industry through decades of execution and invaluable experience in solving incredibly hard manufacturing problems at scale, so one could argue that its customers would push the company to solve the manufacturing problems that its revolutionary designs create and that they would assist it along the way to make sure they have a reliable volume foundry supplier. The same argument could of course be made about Intel and Samsung, but they have some work to do to develop the same reputation for their foundries.

The above might sound a bit speculative, but there is also a technological factor tipping the scales in TSMC’s favor – while designs could be revolutionary, manufacturing advances tend to be evolutionary, so the incumbents should be at an advantage.

Disruption is a ubiquitous threat and a bit of an unknown unknown to most, but a risk/uncertainty nonetheless.

• Concerns about a Chinese invasion of Taiwan;

Lastly, the risk of China invading Taiwan seems to have increased in the minds of Western leaders. This would be, as Jon Stokes puts it, “a catastrophe for China and the world,” primarily because of the potential crippling of TSMC. He explains very well why in this article: https://www.jonstokes.com/p/why-a-chinese-invasion-of-taiwan. Russia’s deranged invasion of Ukraine, however, serves as a reminder that world leaders are very capable of plunging their own countries and the world into catastrophe. When asked about the risk to TSMC of a Chinese invasion, one investor/analyst stated that the investment portfolio wouldn’t be top of mind in such an event, the implication being that the invasion would presage World War III. After reading Jon Stokes’ article, one could envision a more nuanced set of outcomes, though it would be safe to say that the value of TSMC’s business would be significantly and certainly negatively impacted by a China invasion. Out of all listed risks, the probability of a Chinese invasion is most difficult to accurately estimate, but it’s also the one event that, regardless of how it unfolds, will most likely result in a permanent loss of capital.

Conclusion

There are a few very scary-sounding risks ahead for TSMC, including scenarios (the grimmer versions of a Chinese invasion) in which the company could be worth zero, but also significant compounding potential. I leave it up to the readers to consider these risks and to assess whether the current price offers them a sufficiently high discount to their estimate of the sum of the probability-weighted present value of TSMC’s prospective cash flows.